1. Field of the Invention
This invention relates to caching where portions of data are stored in slower main memory and are transferred to a faster memory comprising cache structures between one or more processors and the main memory. For a system with a shared Level 2 (L2) cache(s) memory between the processor(s) and the main memory, an individual L1 cache memory of a processor must first communicate to an associated L2 cache memory system or check with other L2 cache memory systems which may possibly contain a copy of a cache line of data at a given cached location prior to, or upon modification or appropriation of a cache line of data at a given cached location, and includes provisions for notifying the L2 cache memory systems upon determining when the data stored in a particular cache memory location has been replaced.
2. Background Art
In multi-processor systems with a secondary shared cache, e.g., a L2 cache memory, the shared L2 cache memory holds cache lines of data beyond the actual residency of the cache memory in subordinate caches, e.g., a Level 1 (L1) cache memory. This is the value of a secondary L2 cache memory; it contains a superset of all subordinate caches. This reduces traffic from the main memory. Hereinafter, as will be well understood by those skilled in the art, an L1 cache memory may be referred to as an L1 cache and an L2 cache memory may be referred to as an L2 cache; and a cache line of data is referred to as a cache line or a line.
When a processor, e.g., processor A, requests a line for store (“EX” or exclusive request) that line is installed in both the L1 and the L2 caches as exclusive to processor A. When another processor, e.g., processor B, requests the line, processing is elongated if the line is held exclusive to processor A.
However, as is often the case, the central processor A is no longer using the line, and, in fact the line has aged out of the L1 cache and is present only in the L2 cache. Nevertheless, the line is still marked in the L2 cache as being exclusive to the central processor A. Thus extra processing, such as cross investigating and cross invalidating, is required to remove the marking of exclusivity of this line to processor A from the L1 cache and the L2 cache.
In many cases as described here, this line no longer exists in the L1 cache. This unnecessarily elongates the fetch request for another central processor B for the same line, reducing performance. Thus a need exists to speed up this process.